In integrated circuits comprising field-effect transistors, for example, one very important process step is the formation of the gate for each of the transistors, and in particular the dimensions of the gate. In many applications, the performance characteristics, such as switching speed, are functions of the size of the transistor's gate. Thus, for example, a narrower gate tends to produce a higher performance transistor. However, lithographic techniques impose limitations on the width of a resist mask that can be utilized to achieve a desirably narrow gate in a gate etch process.
In an effort to achieve a narrower resist mask than can be attained by lithographic techniques, a resist trim process is generally utilized in the gate etch process. During the resist trim process, the resist material is etched both laterally and vertically to reduce the height and width of the resist mask. After the resist trim process is completed, the rest of the gate stack, which typically includes an anti-reflective coating (“ARC”) layer, a hard mask layer, or a combination ARC layer/hard mask layer over a gate electrode layer, must be etched. When the gate stack includes a hard mask layer, the resist mask must have a sufficient height after the resist trim process to etch the hard mask layer. When the gate stack does not include a hard mask layer, the resist mask must have a sufficient height after the trim process to etch the ARC and gate electrode layers. Thus, a first limit of the resist trim process is determined by the minimum resist height required to overcome erosion during subsequent gate etch steps. A second limit of the resist trim process is determined by the aspect ratio, i.e. height divided by width, of the resist mask during the resist trim process. For example, if the aspect ratio of the resist mask exceeds a certain critical value, the resist mask will collapse or bend, causing failure of the patterning process. As a result, it is difficult to form a resist mask that has a sufficiently narrow width while having a sufficient height to overcome erosion during subsequent gate etch steps.
One attempt to achieve a narrow transistor gate utilizes a silicon oxynitride anti-reflective film in combination with a trim etch process and is disclosed in U.S. Pat. No. 6,107,172, issued on Aug. 22, 2000, titled “Controlled Linewidth Reduction During Gate Pattern Formation Using A SiON BARC.” Another attempt utilizes an organic spin-on bottom anti-reflective coating in combination with a trim etch process to achieve a narrow transistor gate. This attempt is disclosed in U.S. Pat. No. 5,965,461, issued on Oct. 12, 1999, titled “Controlled Linewidth Reduction During Gate Pattern Formation Using A Spin-On BARC.”
Thus, there is a need in the art for a reliable resist mask having a desirably narrow width and sufficient height such that the resist mask can withstand height erosion during subsequent gate etch steps.